512k x 32 static ram cy7c1062av33 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05137 rev. *f revised august 3, 2006 features ?high speed ?t aa = 8 ns ? low active power ? 1080 mw (max.) ? operating voltages of 3.3 0.3v ? 2.0v data retention ? automatic power-down when deselected ? ttl-compatible inputs and outputs ? easy memory expansion with ce 1 , ce 2 , and ce 3 features ? available in non pb-free 119-ball pbga package functional description the cy7c1062av33 is a high-performance cmos static ram organized as 524,288 words by 32 bits. writing to the device is accomplished by enabling the chip (ce 1, ce 2 , and ce 3 low) and forcing the write enable (we ) input low. if byte enable a (b a ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 18 ). if byte enable b (b b ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 18 ). likewise, b c and b d correspond with the i/o pins i/o 16 to i/o 23 and i/o 24 to i/o 31 , respectively. reading from the device is accomplished by enabling the chip (ce 1, ce 2 , and ce 3 low) while forcing the output enable (oe ) low and write enable (we ) high. if the first byte enable (b a ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte enable b (b b ) is low, then data from memory will appear on i/o 8 to i/o 15 . similarly, b c and b d correspond to the third and fourth bytes. see the truth table at the back of this data sheet for a complete description of read and write modes. the input/output pins (i/o 0 through i/o 31 ) are placed in a high-impedance state when t he device is deselected (ce 1, ce 2 or ce 3 high), the outputs are disabled (oe high), the byte selects are disabled (b a-d high), or during a write operation (ce 1, ce 2 , and ce 3 low, and we low). the cy7c1062av33 is available in a 119-ball pitch ball grid array (pbga) package. selection guide ?8 ?10 ?12 unit maximum access time 8 10 12 ns maximum operating current com?l 300 275 260 ma ind?l 300 275 260 maximum cmos standby current com?l/ind?l 50 50 50 ma logic block diagram a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffers 512k x 32 array a 0 a 12 a 14 a 13 a 15 a 16 a 17 a 18 a 10 a 11 i/o 0 ?i/o 31 oe ce 3 b a b d a 9 output buffers control logic b b b c we ce 2 ce 1 [+] feedback [+] feedback
cy7c1062av33 document #: 38-05137 rev. *f page 2 of 9 pin configurations [1, 2] 234567 1 a b c d e f g h j k l m n p r t u i/o 12 i/o 16 i/o 17 i/o 18 i/o 19 i/o 27 i/o 23 i/o 25 aa aa ai/o 0 aa i/o 21 nc i/o 26 i/o 31 i/o 29 i/o 30 b c v ss v ss v dd v dd a v ss a a v dd ce 2 a ce 1 aai/o 1 nc ce 3 b a i/o 2 v ss v ss v ss v dd i/o 4 i/o 6 v ss v dd v dd v ss i/o 8 a aai/o 15 oe v dd v ss v ss v dd v ss v ss v dd v ss b d v ss v dd v ss v ss i/o 5 v dd v ss v ss v ss dnu v ss v dd v ss v ss v ss v ss v dd v ss v ss i/o 10 v dd i/o 14 i/o 13 a a v ss v ss v ss nc b b v dd i/o 3 we a i/o 20 v ss v dd i/o 22 v dd v ss i/o 7 v dd i/o 9 i/o 11 v dd v dd i/o 24 v ss i/o 28 v ss v dd 119-ball pbga v dd (top view) notes: 1. nc pins are not connected on the die. 2. dnu pins have to be left floating or tied to vss to ensure proper application. [+] feedback [+] feedback
cy7c1062av33 document #: 38-05137 rev. *f page 3 of 9 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc to relative gnd [3] .... ?0.5v to +4.6v dc voltage applied to outputs in high-z state [3] ....................................?0.5v to v cc + 0.5v dc input voltage [3] ................................ ?0.5v to v cc + 0.5v current into outputs (low).... ..................................... 20 ma ac test loads and waveforms [5] notes: 3. v il (min.) = ?2.0v for pulse durations of less than 20 ns. 4. tested initially and after any design or proc ess changes that may affect these parameters. 5. valid sram operation does not occur until the power supplies have reached the minimum operating v dd (3.0v). as soon as 1 ms (t power ) after reaching the minimum operating v dd , normal sram operation can begin including reduction in v dd to the data retention (v ccdr , 2.0v) voltage. operating range range ambient temperature v cc commercial 0 c to +70 c 3.3v 0.3v industrial ?40 c to +85 c dc electrical characteristics over the operating range parameter description test conditions ?8 ?10 ?12 unit min. max. min. max. min. max. v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 v v ih input high voltage 2.0 v cc + 0.3 2.0 v cc + 0.3 2.0 v cc + 0.3 v v il input low voltage [3] ?0.3 0.8 ?0.3 0.8 ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ?1 +1 ?1 +1 a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ?1 +1 ?1 +1 a i cc v cc operating supply current v cc = max., f = f max = 1/t rc com?l 300 275 260 ma ind?l 300 275 260 ma i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max 70 70 70 ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 com?l/ ind?l 50 50 50 ma capacitance [4] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 8 pf c out i/o capacitance 10 pf 90% 10% 3.3v gnd 90% 10% all input pulses 3.3v output 5 pf *including jig and scope output (a) (b) r1 317 ? 167 ? r2 351 ? venin equivalent th 1.73v rise time > 1 v/ns fall time: > 1 v/ns (c) output 50 ? z 0 = 50 ? v th = 1.5v 30 pf including all components of test equipment * [+] feedback [+] feedback
cy7c1062av33 document #: 38-05137 rev. *f page 4 of 9 ac switching characteristics over the operating range [6] parameter description ?8 ?10 ?12 unit min. max. min. max. min. max. read cycle t power v cc (typical) to the first access [7] 111 ms t rc read cycle time 8 10 12 ns t aa address to data valid 8 10 12 ns t oha data hold from address change 3 3 3 ns t ace ce 1 , ce 2 , or ce 3 low to data valid 8 10 12 ns t doe oe low to data valid 5 5 6 ns t lzoe oe low to low-z [8] 111 ns t hzoe oe high to high-z [8] 556 ns t lzce ce 1 , ce 2 , or ce 3 low to low-z [8] 333 ns t hzce ce 1 , ce 2 , or ce 3 high to high-z [8] 556 ns t pu ce 1 , ce 2 , or ce 3 low to power-up [9] 000 ns t pd ce 1 , ce 2 , or ce 3 high to power-down [9] 81012 ns t dbe byte enable to data valid 5 5 6 ns t lzbe byte enable to low-z [8] 111 ns t hzbe byte disable to high-z [8] 556 ns write cycle [10, 11] t wc write cycle time 8 10 12 ns t sce ce 1 , ce 2 , or ce 3 low to write end 6 7 8 ns t aw address set-up to write end 6 7 8 ns t ha address hold from write end 0 0 0 ns t sa address set-up to write start 0 0 0 ns t pwe we pulse width 6 7 8 ns t sd data set-up to write end 5 5.5 6 ns t hd data hold from write end 0 0 0 ns t lzwe we high to low-z [8] 333 ns t hzwe we low to high-z [8] 556 ns t bw byte enable to end of write 6 7 8 ns data retention waveform notes: 6. test conditions assume signal transition ti me of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and transmission line loads. test conditions for the read cycl e use output loading as shown in (a) of ac test loads, unless sp ecified otherwise. 7. this part has a voltage regulator that steps down the voltage from 3v to 2v internally. t power time has to be provided initially before a read/write operation is started. 8. t hzoe , t hzce , t hzwe , t hzbe , and t lzoe , t lzce , t lzwe , and t lzbe are specified with a load capacitance of 5 pf as in (b) of ac test loads. transition is measured 200 mv from steady-state voltage. 9. these parameters are guaranteed by design and are not tested. 10. the internal write time of the memory is defined by the overlap of ce 1 low, ce 2 high, ce 3 low, and we low. the chip enables must be active and we must be low to initiate a write, and the transition of any of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 11. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce v cc [+] feedback [+] feedback
cy7c1062av33 document #: 38-05137 rev. *f page 5 of 9 switching waveforms read cycle no. 1 [12, 13] read cycle no. 2 (oe controlled) [13, 14] notes: 12. device is continuously selected. oe , ce , b a , b b , b c , b d = v il . 13. we is high for read cycle. 14. address valid prior to or coincident with ce transition low. previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd high oe ce 1 ,ce 2 ,ce 3 icc i sb impedance address data out v cc supply t dbe t lzbe t hzce b a , b b , b c , b d current i cc [+] feedback [+] feedback
cy7c1062av33 document #: 38-05137 rev. *f page 6 of 9 write cycle no. 1 (ce controlled) [15, 16, 17] write cycle no. 2 (ble or bhe controlled) [15, 16, 17] notes: 15. ce indicates a combination of all three chip enables. when active low, ce indicates the ce 1 , ce 2 , and ce 3 are low. 16. data i/o is high-impedance if oe or b a , b b , b c , b d = v ih . 17. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw datai/o address ce we t b a , b b , b c , b d t hd t sd t bw t sa t ha t aw t pwe t wc t sce datai/o address we ce b a , b b , b c , b d [+] feedback [+] feedback
cy7c1062av33 document #: 38-05137 rev. *f page 7 of 9 write cycle no. 3 (we controlled, oe low) truth table ce 1 ce 2 ce 3 oe we b a b b b c b d i/o 0 ? i/o 7 i/o 8 ? i/o 15 i/o 16 ? i/o 23 i/o 24 ? i/o 31 mode power h x x x x x x x x high-z high-z high-z high-z power down (i sb ) x h x x x x x x x high-z high-z high-z high-z power down (i sb ) x x h x x x x x x high-z high-z high-z high-z power down (i sb ) l l l l h l l l l data out data out data out data out read all bits (i cc ) l l l l h l h h h data out high-z high-z high-z read byte a bits only (i cc ) l l l l h h l h h high-z data out high-z high-z read byte b bits only (i cc ) l l l l h h h l h high-z high-z data out high-z read byte c bits only (i cc ) l l l l h h h h l high-z high-z high-z data out read byte d bits only (i cc ) l l l x l l l l l data in data in data in data in write all bits (i cc ) l l l x l l h h h data in high-z high-z high-z write byte a bits only (i cc ) l l l x l h l h h high-z data in high-z high-z write byte b bits only (i cc ) l l l x l h h l h high-z high-z data in high-z write byte c bits only (i cc ) l l l x l h h h l high-z high-z high-z data in write byte d bits only (i cc ) l l l h h x x x x high-z high-z high-z high-z selected, outputs disabled (i cc ) switching waveforms (continued) t hd t sd t sce t ha t aw t pwe t wc t bw data i/o address ce we t sa t lzwe t hzwe b a , b b , b c , b d [+] feedback [+] feedback
cy7c1062av33 document #: 38-05137 rev. *f page 8 of 9 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all product and company names mentio ned in this document may be the tr ademarks of their respective holders. ordering information speed (ns) ordering code package name package type operating range 8 cy7c1062av33-8bgc 51-85115 119 -ball (14 x 22 x 2.4 mm) pbga commercial 10 cy7c1062av33-10bgc cy7c1062av33-10bgi industrial 12 CY7C1062AV33-12BGC commercial cy7c1062av33-12bgi industrial package diagram 51-85115-*b 119-ball pbga (14 x 22 x 2.4 mm) (51-85115) [+] feedback [+] feedback
cy7c1062av33 document #: 38-05137 rev. *f page 9 of 9 document history page document title: cy7c1062av33 512k x 32 static ram document number: 38-05137 rev. ecn no. issue date orig. of change description of change ** 109752 02/27/02 hgk new data sheet *a 117059 09/19/02 dfp removed 15-ns bin and added 8-ns bin. changed ce 2 to ce 2 . changed c in ? input capacitance ? from 6 pf to 8 pf. changed c out ? output capacitance ? from 8 pf to 10 pf. *b 119389 10/07/02 dfp updated i cc , t sd , and t doe parameters. removed note 7 (i z /h z comment). *c 120384 11/13/02 dfp final data sheet. removed note 2. added note 3 to ?ac test loads and waveforms? and note 7 to t pu and t pd . *d 124440 2/25/03 meg changed isb1 from 100 ma to 70 ma *e 329638 see ecn rkf removed ce 2 waveform showing active high signal timing on page #5, and included it with the ce 1 , ce 3 waveform corrected truth table on page 7 with ce 2 active low information *f 492137 see ecn nxr included note #1 and 2 on page #2 changed the description of i ix from input load current to input leakage current in dc electrical characteristics table updated ordering information table [+] feedback [+] feedback
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